MIC5166 3A High-Speed, Low-VIN DDR Terminator Features General Description * Operating Voltage Range: - VDDQ Supply: 0.9V to 3.6V - Bias Supply: 2.5V to 5.5V * High Bandwidth: Very Fast Transient Response * Stable with Two 10 F Ceramic Output Capacitors * Two 10 F Output Capacitors used in Most Applications * High Output Voltage Accuracy: - 0.015% Line Regulation - 1.5% Load Regulation * Logic Level Enable Input * Power Good (PG) * Thermally Enhanced 3 mm x 3 mm DFN * Junction Temperature Range -40C to +125C * This Device Meets DDR4 Requirements The MIC5166 is a 3A, high-speed, linear, low VIN, double data rate (DDR), memory terminator power supply. The part is small and requires small output capacitors, making it a tiny overall solution. This allows it to be conveniently placed close to the DDR memory, minimizing circuit board layout inductance that may cause excessive voltage ripple at the DDR memory. Applications * * * * * Desktop Computers Notebook Computers Datacom Systems Servers Video Cards The MIC5166 contains a precision voltage divider network in order to take in the VDDQ voltage as a reference voltage and conveniently output the terminator voltage (VTT) at one half of the VDDQ input voltage. The MIC5166 is capable of sinking and sourcing up to 3A. It is stable with only two 10 F ceramic output capacitors. The part is available in a small 3 mm x 3 mm DFN thermally-enhanced package. The MIC5166 has a high-side NMOS output stage offering very low output impedance, and very high bandwidth. The NMOS output stage offers a unique ability to respond very quickly to sudden load changes such as is required for DDR memory termination power supply applications. Package Type MIC5166 10-Lead 3 mm x 3 mm DFN (ML) (Top View) 2018 - 2019 Microchip Technology Inc. VREF 1 10 VIN BIAS 2 9 VTT AGND 3 8 PGND VDDQ 4 7 EN PG 5 6 SNS EP DS20006085B-page 1 MIC5166 Typical Application Circuit MIC5166 VBIAS 2.5V TO 5.5V 2 BIAS VDDQ 4.7F 1.0F VIN 0.9V TO 3.6V 10N 10 10F 8 7 EN VTT VIN SNS 5 PG VDDQ 0.9V TO 3.6V 4 PGND PG EN 6 22F EP AGND VREF VTT 3A 9 3 VREF 10mA 1 1.0F Functional Block Diagram MIC5166 VBIAS 2.5V TO 5.5V BIAS UVLO 1F UVLO EN CONTROL LOGIC EN VIN 0.9V TO 3.6V VIN 10F THERMAL SHUTDOWN VTT VTT 3A 2x10F EP VDDQ 0.9V TO 3.6V VDDQ 4.7F PGND 45N SNS 5N 110% VREF VBIAS VREF 10N 1 .0F 5N PG 90% VREF PG 45N AGND DS20006085B-page 2 2018 - 2019 Microchip Technology Inc. MIC5166 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VBIAS ............................................................................................................................................................ -0.3V to +6V VIN .............................................................................................................................................................. -0.3V to VBIAS VDDQ ..............................................................................................................................................................-0.3V to VIN VTT .................................................................................................................................................................-0.3V to VIN VEN ............................................................................................................................................................. -0.3V to VBIAS VPG............................................................................................................................................................. -0.3V to VBIAS PGND to AGND ........................................................................................................................................ -0.3V to +0.3V Junction Temperature (TJ)..................................................................................................................................... +150C Storage Temperature (TS)...................................................................................................................... -65C to +150C Lead Temperature (Soldering, 10 sec.)................................................................................................................. +260C Continuous Power Dissipation (TA = +25C; De-Rated 16.4 mW/C above 25C).................................................1.64W Continuous Power Dissipation (TA = +85C) .......................................................................................................656 mW ESD Rating (HBM, Note 1) ........................................................................................................................................ 2 kV Operating Ratings Supply Voltage (VBIAS).............................................................................................................................. +2.5V to +5.5V Supply Voltage (VIN, Note 2)..................................................................................................................... +0.9V to +3.6V Supply Voltage (VDDQ, Note 3)...................................................................................................................... +0.9V to VIN Power Good Voltage (VPG) ............................................................................................................................. 0V to VBIAS Enable Input Voltage (VEN) ............................................................................................................................. 0V to VBIAS Junction Temperature Range (TJ) .......................................................................................................... -40C to +125C Package Thermal Resistance 3 mm x 3 mm DFN (JC) ....................................................................................................................................28.7C/W 3 mm x 3 mm DFN (JA) ....................................................................................................................................60.7C/W Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. Notice: The device is not guaranteed to function outside its operating ratings. Note 1: Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5 k in series with 100 pF. 2: If VBIAS 3.6V, then VIN(MAX) = VBIAS. 3: If VBIAS 4V, then VDDQ(MAX) = 2 x (VBIAS - 2.2V). If VBIAS > 4V, then VDDQ(MAX) = 3.6V. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 3 MIC5166 ELECTRICAL CHARACTERISTICS Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25C, unless noted. Bold values indicate -40C TJ +125C. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Input Voltage Range VIN 0.9 -- 3.6 V -- Undervoltage Lockout Trip Level -- 0.625 0.8 0.9 V VIN rising UVLO Hysteresis -- -- 150 -- mV -- Quiescent Supply Current IIN -- 0.1 10 A IOUT = 0A ISHDN -- 0.1 5 A VEN = 0V VBIAS 2.5 -- 5.5 V -- Undervoltage Lockout Trip Level -- 1.9 2.23 2.33 V VBIAS rising UVLO Hysteresis -- -- 70 -- mV -- 1.6 3 -- 1.6 3 Power Input Supply Shutdown Current Bias Supply Bias Voltage Range mA -- IOUT = 1 mA Quiescent Supply Current IBIAS Shutdown Current ISHDN -- 0.1 5 A VEN = 0V VTT Accuracy -- -25 -- 25 mV Variation from VREF, IOUT = -2A to 2A Load Regulation -- -- 1.5 2.1 -1.8 -1.4 -- -0.05 0.005 0.05 -0.1 0.015 0.17 -1 -- 1 -- 1.15 -- -- 1.25 -- -- 1.65 2.2 IOUT = 1A VTT Output Line Regulation -- % %/V VSNS = 0.75V, IOUT = +10 mA to +3A VSNS = 0.75V, IOUT = -10 mA to -3A VIN = 1.5V to 3.6V, VBIAS = 5.5V, IOUT = 100 mA VIN = 1.5V, VBIAS = 2.5V to 5.5V, IOUT = 100 mA VREF Output VREF Voltage Accuracy VREF % Variation from (VDDQ/2), IREF = -10 mA to 10 mA, VREF Output = 0.6V (DDR4), IOUT = 0A. Bias Supply Dropout Voltage Dropout Voltage (VBIAS - VTT) VDO IOUT = 100 mA V IOUT = 500 mA IOUT = 3A Enable Control EN Logic High Level VIH 1.2 -- -- EN Logic Low Level VIL -- -- 0.2 EN Current IEN -- 1.0 -- -- 6.0 -- Start-Up Time tSU -- 55 -- Note 1: V A s Logic high Logic low VEN = 0.2V VEN = 1.2V From EN pin going high to VTT 90% of VREF Specification for packaged product only. DS20006085B-page 4 2018 - 2019 Microchip Technology Inc. MIC5166 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: VIN = 1.5V, VBIAS = 3.3V, VDDQ = 1.5V, TA = +25C, unless noted. Bold values indicate -40C TJ +125C. Note 1 Parameter Sym. Min. Typ. Max. Units Conditions Sourcing Current Limit ILIM 3.1 4.9 7.8 A VIN = 2.7V, VTT = 0V Sinking Current Limit ILIM -3.1 -4.9 -7.8 A VIN = 2.7V, VTT = VIN Top MOSFET RDS(ON) -- 130 190 m Source, IOUT = 3A (VTT to PGND) Bottom MOSFET RDS(ON) -- 130 190 m Sink, IOUT = -3A (VIN to VTT) PG Window -- 90 -- 110 % Threshold percent of VTT from VREF Hysteresis -- -- 2 -- % -- PG Output Low Voltage -- -- 430 -- mV IPG = 4 mA (sinking) PG Leakage Current -- -- -- 1.0 A VPG = 5.5V, VSNS = VREF Overtemperature Shutdown -- -- 150 -- C TJ rising Overtemperature Shutdown Hysteresis -- -- 10 -- C -- Short-Current Protection Internal FETs Power Good (PG) Thermal Protection Note 1: Specification for packaged product only. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 5 MIC5166 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units TJ -40 -- +125 C Conditions Temperature Ranges Junction Temperature Range Maximum Junction Temperature -- TJ(MAX) -- -- +150 C -- Lead Temperature -- -- -- +260 C Soldering, 10 sec. Storage Temperature Range TS -65 -- +150 C -- Thermal Resistance, 3x3 DFN 10-Ld JC -- 28.7 -- C/W -- Thermal Resistance, 3x3 DFN 10-Ld JA -- 60.7 -- C/W -- Package Thermal Resistances Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125C rating. Sustained junction temperatures above +125C can impact the device reliability. DS20006085B-page 6 2018 - 2019 Microchip Technology Inc. MIC5166 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. FIGURE 2-1: VIN Operating Supply Current vs. Input Voltage. FIGURE 2-4: VBIAS Operating Supply Current vs. BIAS Voltage. FIGURE 2-2: Input Voltage. VIN Shutdown Current vs. FIGURE 2-5: BIAS Voltage. VBIAS Shutdown Current vs. FIGURE 2-3: vs. VDDQ Voltage. VREF/VDDQ Tracking Ratio FIGURE 2-6: vs. BIAS Voltage. VREF/VDDQ Tracking Ratio 2018 - 2019 Microchip Technology Inc. DS20006085B-page 7 MIC5166 FIGURE 2-7: Voltage. Enable Threshold vs. Input FIGURE 2-10: Top MOSFET On-Resistance vs. Input Voltage. FIGURE 2-8: Voltage. Enable Pin Current vs. Input FIGURE 2-11: Bottom MOSFET On-Resistance vs. Input Voltage. FIGURE 2-9: Power Good Window/VTT Ratio vs. Input Voltage. DS20006085B-page 8 FIGURE 2-12: Voltage. Current Limit vs. Input 2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-13: Voltage. Load Regulation vs. Input FIGURE 2-16: VREF/VDDQ vs. I_Load. FIGURE 2-14: VREF - VTT vs. I_Load. FIGURE 2-17: VTT/VDDQ vs. I_Load. FIGURE 2-15: VTT vs. I_Load. FIGURE 2-18: VIN Operating Supply Current vs. Temperature. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 9 MIC5166 FIGURE 2-19: Temperature. VIN Shutdown Current vs. FIGURE 2-22: vs. Temperature. Sourcing Load Regulation FIGURE 2-20: Temperature. VIN UVLO Threshold vs. FIGURE 2-23: Temperature. Sinking Load Regulation vs. FIGURE 2-21: Temperature. Enable Threshold vs. FIGURE 2-24: vs. Temperature. VREF/VDDQ Tracking Ration DS20006085B-page 10 2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-25: Temperature. Output Voltage vs. FIGURE 2-28: Top MOSFET On-Resistance vs. Temperature. FIGURE 2-26: Temperature. Current Limit vs. FIGURE 2-29: Bottom MOSFET On-Resistance vs. Temperature. FIGURE 2-27: Temperature. Enable Pin Current vs. FIGURE 2-30: 2018 - 2019 Microchip Technology Inc. EN Turn-On. DS20006085B-page 11 MIC5166 FIGURE 2-31: EN Turn-Off. FIGURE 2-34: VBIAS Turn-On (UVLO). FIGURE 2-32: VIN Turn-On (UVLO). FIGURE 2-35: VBIAS Turn-Off (UVLO). FIGURE 2-33: VIN Turn-Off UVLO. FIGURE 2-36: Load Transient (3A). DS20006085B-page 12 2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 2-37: Line Transient. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 13 MIC5166 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name Description 1 VREF Reference Voltage. This output provides an output of the internal reference voltage VDDQ/2. The VREF output is used to provide the reference voltage for the memory chip. Connect a 1.0 F capacitor to ground at this pin. This pin can sink and source 10 mA. 2 BIAS BIAS Supply Voltage. The BIAS supply is the power MOSFET gate drive supply voltage and the supply bus for the IC. The BIAS voltage must be greater than (VTT + 2.2V). A 1.0 F ceramic capacitor from the BIAS pin to PGND must be placed next to the IC. 3 AGND Analog Ground. Internal signal ground for all low-power circuits. 4 VDDQ Input Supply. VDDQ is connected to an internal precision divider that provides the VREF. Connect a 4.7 F capacitor to ground at this pin. Power Good. This is an open-drain output that indicates when the output voltage is within 10% of the reference voltage. The PG flag is asserted typically with 65 s delay when the enable is set low or when the output goes outside 10% the window threshold. 5 PG 6 SNS 7 EN Enable. Logic level control of the output. Logic high enables the MIC5166 and a logic low shuts down the MIC5166. In the off state, supply current of the device is greatly reduced (typically 0.2 A). The EN pin should not be left open. 8 PGND Power Ground. Internal ground connection to the source of the internal, low-side drive, N-channel MOSFET. 9 VTT Power Output. This is the connection to the source of the internal high-side N-channel MOSFET and drain of the low-side N-channel MOSFET. This is a high-frequency, high-power connection, therefore two 10 F output capacitors must be placed as close to the IC as possible. 10 VIN High-Side N-Channel MOSFET Drain Connection. The VIN operating voltage range is from 0.9V to 3.6V. An input capacitor between the VIN pin and the PGND is required as close to the chip as possible. EP ePAD DS20006085B-page 14 Feedback. Input to the error amplifier. Exposed Pad. Must be connected to a GND plane for best thermal performance. 2018 - 2019 Microchip Technology Inc. MIC5166 4.0 FUNCTIONAL DIAGRAM 4.1 DDR memory requires two power supplies: one for the memory chip, referred to as VDDQ, and the other for a termination supply, VTT, which is one-half VDDQ. With memory speeds in excess of 300 MHz, the memory system bus must be treated as a transmission line. To maintain good signal integrity the memory bus must be terminated to minimize signal reflections. Figure 4-1 shows the simplified termination circuit. Each control, address and data lines have these termination resistors RS and RT connected to them. VDDQ 1.8V + VDDQ VDDQ DDR MEMORY CHIP SET RS + RT VDDQ RS - VREF RT + MIC5166 VBIAS BIAS VDDQ 1.0F 4.7F VIN 10F 10N PGND PG PG EN EN FIGURE 4-1: Circuit. VTT SNS EP AGND 22F VTT is regulated to VREF. Due to high-speed signaling, the load current seen by VTT is constantly changing. To maintain adequate transient response, two 10 F ceramic capacitors are required. The proper placement of ceramic capacitors is important to reduce both ESR and ESL such that high-current and high-speed transients do not exceed the dynamic voltage tolerance requirement of VTT. The ceramic capacitors provide current during the fast edges of the bus transition. Using several smaller ceramic capacitors distributed near the termination resistors is important to reduce the effects of PCB trace inductance. 4.2 1.0F DDR Memory Termination Bus termination provides a means to increase signaling speed while maintaining good signal integrity. The termination network consists of a series resistor (RS) and a terminating resistor (RT). Values of RS range between 10 to 30 with a typical of 22, while RT ranges from 22 to 28 with a typical value of 25. VREF must maintain half VDDQ with a 1% tolerance, while VTT will dynamically sink and source current to maintain a termination voltage of 40 mV from the VREF line under all conditions. This method of bus termination reduces common-mode noise, settling time, voltage swings, EMI/RFI, and improves slew rates. VDDQ powers all the memory ICs, memory drivers and receivers for all the memory bits in the DDR memory system. The MIC5166 regulates VTT to VDDQ/2 during sourcing or sinking current. The memory bits are not usually all at a logic high or logic low at the same time, so the VTT supply is usually not sinking or sourcing -3A or +3A current continuously. 2018 - 2019 Microchip Technology Inc. VDDQ The VDDQ input on the MIC5166 is used to create the internal reference voltage for VTT. The reference voltage is generated from an internal resistor divider network of two 500 k resistors, generating a reference voltage VREF that is VDDQ/2. The VDDQ input should be Kelvin connected as close as possible to the memory supply voltage. Because the reference is simply VDDQ/2, any perturbations on VDDQ will also appear at half the amplitude on the reference. For this reason, a 4.7 F ceramic capacitor is required on the VDDQ supply. This will aid performance by improving the source impedance over a wide frequency range. 4.3 VREF VTT Sense The sense (SNS) pin provides the path for the error amplifier to regulate VTT. The SNS input must also be Kelvin connected to the VTT bypass capacitors. If the SNS input is connected too close to the MIC5166, the IR drop of the PCB trace can cause the VTT voltage at the memory chip to be too low. Placing the MIC5166 as close as possible to the DDR memory will improve the load regulation performance. 4.4 Enable The MIC5166 features an active-high enable input (EN) that allows on-off control of the regulator. The current through the device reduces to near "zero" when the device is shutdown, with only <0.2 A of leakage current. The EN input may be directly tied to VBIAS. The active-high enable pin uses CMOS technology and the enable pin cannot be left floating. A floating enable pin may cause an indeterminate state on the output. 4.5 Power Good (PG) The power good (PG) output provides an undervoltage and overvoltage fault flag for the VTT output. The PG output remains high as long as VTT is within 10% range of VREF and goes low if the output moves beyond this range. DS20006085B-page 15 MIC5166 1.10*VREF 1.08*VREF 0.90*VREF 0.88*VREF VREF 0V PG 0V FIGURE 4-2: Power Good Threshold. The PG has an open-drain output. A pull-up resistor must be connected to VBIAS, VIN, or an external source. The external source voltage must not exceed the maximum rating of the pin. The PG pin can be connected to another regulator's enable pin for sequencing of the outputs. 4.6 VBIAS Requirement A 1 F ceramic input capacitor is required on the VBIAS pin. To achieve the ultra-fast transient response, the MIC5166 uses an all N-channel power output stage as shown in the Functional Block Diagram. The high-side N-channel MOSFET requires the VBIAS voltage to be 2.2V higher than the VTT to be able to fully enhance the high-side MOSFET. 4.7 VIN Requirement VIN is used to supply the rail voltage for the high-side N-channel power output stage. It is normally connected to VDDQ, but it can be connected to a lower voltage to reduce power dissipation. In this case, the input voltage must be higher than the VTT voltage to ensure that the output stage is not operating in dropout. DS20006085B-page 16 2018 - 2019 Microchip Technology Inc. MIC5166 5.0 COMPONENT SELECTION 5.1 Input Capacitor A 10 F ceramic input capacitor is all that is required for most applications if it is close to a bulk capacitance. The input capacitor must be placed on the same side of the board and next to the MIC5166 to minimize the dropout voltage and voltage ringing during transient and short-circuit conditions. It is also recommended that each capacitor to be connected to the PGND directly, not through vias. X7R or X5R dielectric ceramic capacitors are recommended because of their temperature performance. X7R-type capacitors change capacitance by 15% over their operating temperature range and are the most stable type of ceramic capacitors. Z5U and Y5V dielectric capacitors change value by as much as 50% and 60% respectively over their operating temperature ranges. To use a ceramic chip capacitor with Y5V dielectric, the value must be much higher than an X7R ceramic. 5.2 EQUATION 5-1: P D = V IN - V TT I OUT + V BIAS I GND Where: IOUT = Approximated by using numbers from the Electrical Characteristics or Typical Performance Curves. For example, given an expected maximum ambient temperature (TA) of 70C with VIN = 1.2V, VBIAS = 3.3V, VTT = 0.9V, and IOUT = 3A, first calculate the expected PD using Equation 5-1: EQUATION 5-2: P D = 1.2V - 0.9V 3A + 3.3V 0.0016A = 0.90528W Output Capacitor As part of the frequency compensation, the MIC5166 requires two 10 F ceramic output capacitors for best transient performance. To improve transient response, any other type of capacitor can be placed in parallel as long as the two 10 F ceramic output capacitors are placed next to the MIC5166. Next, determine the junction temperature for the expected power dissipation above using the thermal resistance (JA) of the 10-pin 3 mm x 3 mm DFN (YML) adhering to the following criteria for the PCB design (1oz. copper and 100 mm2 copper area for the MIC5166): The output capacitor type and placement criteria are the same as the input capacitor. See the Input Capacitor section for a detailed description. EQUATION 5-3: 5.3 Thermal Considerations The MIC5166 is packaged in the 3 mm x 3 mm DFN, a package that has excellent thermal performance. This maximizes heat transfer from the junction to the exposed pad (ePAD) that connects to the ground plane. The size of the ground plane attached to the exposed pad determines the overall thermal resistance from the junction to the ambient air surrounding the printed circuit board. 5.4 Thermal Design The most complicated design parameters to consider are thermal characteristics. Thermal design requires the following application-specific parameters: * * * * * Maximum ambient temperature (TA) Output current (IOUT) Output voltage (VOUT) Input voltage (VIN) Ground current (IGND) First, calculate the power dissipation of the regulator from these numbers and the device parameters from this data sheet. 2018 - 2019 Microchip Technology Inc. T J = JA P D + T A T J = 60.7C/W 0.90528W + 70C T J = 124.95C To determine the maximum power dissipation allowed that would not exceed the IC's maximum junction temperature (125C) when operating at a maximum ambient temperature of 70C: EQUATION 5-4: P D MAX = T J MAX - T A JA P D MAX = 125C - 70C 60.7C/W = 0.9061W DS20006085B-page 17 MIC5166 5.5 Thermal Measurements It is always wise to measure the IC's case temperature to make sure that it is within its operating limits. Although this might seem like a very elementary task, it is very easy to get erroneous results. The most common mistake is to use the standard thermocouple that comes with the thermal voltage meter. This thermocouple wire gauge is large, typically 22 gauge, and behaves like a heat sink, resulting in a lower case measurement. There are two suggested methods for measuring the IC case temperature: a thermocouple or an infrared thermometer. If a thermocouple is used, it must be constructed of 36 gauge wire or higher to minimize the wire heat sinking effect. In addition, the thermocouple tip must be covered in either thermal grease or thermal glue to make sure that the thermocouple junction makes good contact to the case of the IC. This thermocouple from Omega (5SC-TT-K-36-36) is adequate for most applications. To avoid this messy thermocouple grease or glue, an infrared thermometer is recommended. Most infrared thermometers' spot size is too large for an accurate reading on small form factor ICs. However, an IR thermometer from Optris has a 1 mm spot size, which makes it ideal for the 3 mm x 3 mm DFN package. 5.6 Sequencing The following diagrams illustrate methods for connecting MIC5166s to achieve sequencing requirements: MIC22705 VIN 5.0V 4N 22F x4 PVIN SVIN PGND 1.0H SW EP SGND PG1 PG EN1 EN/DLY DELAY RC COMP 47F x2 VDDQ 1.8V/7A R1 1.10N FB 3.3nF R2 69 39pF 20N MIC5166 BIAS VDDQ 1.0F VDDQ 4.7F VIN 10F PGND EN2 EN PG2 PG VTT 0.9V/3A VTT SNS EP AGND 22F VREF 1.0F VREF 10mA EN/EN2 VDDQ VTT VIN = 5V VDDQ = 1.8V VTT = 0.9V IOUT1 = 1A IOUT2 = 1A RC = 3.3nF Time (4ms/div) FIGURE 5-1: Turn-On Sequence with Soft-Start (RC = 3.3 nF). DS20006085B-page 18 2018 - 2019 Microchip Technology Inc. MIC5166 MIC22705 1.0H VIN 5.0V N 22F x4 PVIN SVIN PGND SW 47F x2 EP SGND PG1 PG EN1 EN/DLY DELAY RC COMP VDDQ 1.8V/7A R1 N FB R2 39pF N MIC5166 BIAS VDDQ 4.7F 1.0F VIN VDDQ 10F PGND EN2 EN PG2 PG VTT 0.9V/3A VTT SNS 22F EP AGND VREF 1.0F VREF 10mA EN/EN2 VDDQ VTT VIN = 5V VDDQ = 1.8V VTT = 0.9V IOUT1 = 1A IOUT2 = 1A RC = OPEN Time (4ms/div) FIGURE 5-2: Turn-On Sequence without Soft-Start (RC = Open). 2018 - 2019 Microchip Technology Inc. DS20006085B-page 19 MIC5166 6.0 PCB LAYOUT GUIDELINES To minimize EMI and output noise, follow these layout recommendations. PCB layout is critical to achieve reliable, stable, and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal, and return paths. The following guidelines should be followed to ensure proper operation of the MIC5166 converter. 6.1 IC * The 10 F ceramic capacitor, which is connected to the VIN pin, must be located right at the IC. The VDDQ pin is very noise sensitive and placement of the capacitor is very critical. Use wide traces to connect to the VDDQ and AGND pins. * The signal ground pin (AGND) must be connected directly to the ground planes. Do not route the AGND pin to the PGND Pad on the top layer. * Place the IC close to the point-of-load (POL). * Use wide traces to route the input and output power lines. * Signal and power grounds should be kept separate and connected at only one location. 6.2 6.3 Output Capacitor * Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. * Phase margin will change as the output capacitor value and ESR changes. Contact the factory if the output capacitor is different from what is shown in the BOM. * The feedback divider network must be place close to the IC with the bottom of R2 connected to AGND. * The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high current load trace can degrade the DC load regulation. Input Capacitor * A 10 F X5R or X7R dielectric ceramic capacitor is recommended on each of the VIN pins for bypassing. * Place the input capacitors on the same side of the board and as close to the IC as possible. * Keep both the VIN pin and PGND connections short. * Place several vias to the ground plane close to the input capacitor ground terminal. * Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors. * Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor. * If a Tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%. * In hot-plug applications, a Tantalum or Electrolytic bypass capacitor must be used to limit the overvoltage spike seen on the input supply with power is suddenly applied. DS20006085B-page 20 2018 - 2019 Microchip Technology Inc. MIC5166 EVALUATION BOARD SCHEMATICS J2 C3 2.2F/6.3V R4 47.5K 1 18 C4 1nF 20 C6 1nF RC 19 C5 OPEN FB RC DELAY 9 FIGURE 7-1: VIN C14 100F/6.3V R9 10k VDDQ J8 R11 2.2 J10 11 16 5 R1C 1.1K R1A 1.1K R1B 1.1K CF 2 3 3 COMP 4 C9 100pF R1D 1.1K R2 698 C7 39pF 5 7 R3 20K C8 390pF C15 10F/6.3V U2 MIC5166YMM 10 1 VREF VIN 2 VBIAS VTT 9 3 AGND PGND 4 VDDQ EN 5 PG 1 TP9 C16 1F/6.3V C17 4.7F C18 1F VSNS EP C24 10F/6.3V VTT R10 1k 8 TP10 7 6 R12 0 3 TP11 C19 22F/6.3V J9 GND J7 FIGURE 7-2: 6 VBIAS R8 2.2 GND TP18 TP19 TP20 TP21 C12 1nF/50V VIN J5 5VIN PG C11 47F/6.3V U1 Schematic. TP1 VDDQ C10 47F/6.3V EN 9 TP7 POR VIN L1 1H 12 SW 13 SW 14 SW 15 SW 10 PVIN 17 PVIN 8 SVIN SGND R6 1 TP4 SW U1 MIC22405YML C2 22F 5VIN 1 5V_INPUT R7 49.9 C1 22F/6.3V C13 470F/10V 2 PGND PGND PGND 7.0 U2 Schematic. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 21 FIGURE 7-3: DS20006085B-page 22 3 2 R19 1K 10K RV1 C22 0.1F 1 5 1 OUT T/T GND 2 U4 MIC1557YM5 CS VS 3 4 R20 100K SINK SOURCE C21 1F CLK_IN VBIAS J15 BIAS 1 2 TP13 3 1 2 TP15 2 1 1 TP16 R18 100K R16 100K 2B 2A 13 4B 9 3A 10 3B 12 4A 5 4 2 1B 1 1A U3 4Y 3Y 11 8 2Y 6 1Y 3 C23 1F GND 7 SN74AHCT00 14 VCC VBIAS C20 10F J14 3 4 2 6 VBIAS GND INB INA VS U5 MIC4425 NC OUTB OUTA NC 8 5 7 1 R21 2.2 R14 R22 0.5 R23 0.5 1, 2, 3 4 4, 5, 6, 7, 8 1, 2, 3 4, 5, 6, 7, 8 R13 VIN VTT Q4 SIR172DP TP14 R24 TP23 1 Q3 SIR172DP TP22 R15 J6 VTT MIC5166 Evaluation Board Schematic. 2018 - 2019 Microchip Technology Inc. MIC5166 TABLE 7-1: BILL OF MATERIALS Item C1, C2, C19 C3 Part Number 08056D226MAT C2012X5R0J226K GRM21BR60J226ME39L C7 AVX GRM188R71H102KA01D C9 C14 06036D475KAT2A C5 C13 L1 Q3, Q4 TDK EEU-FC1A471 FP3-1R0-R NDS8425 47F, 6.3V, ceramic capacitor, X5R,1206 2 100 F, 6.3V, ceramic capacitor, X5R, 1210 1 10 F, 6.3V, ceramic capacitor, X5R, 0603 3 1 F, 6.3V, ceramic capacitor, X5R, 0603 4 4.7 F, 6.3V, ceramic capacitor, X5R, 0603 1 N.U. 0603 ceramic capacitor 1 0.1 F, 50V, ceramic capacitor, X7R, 0603 1 470 F/10V, Elect., 20%, 8x11.5, Radial 1 1 H,6.26A Inductor 1 AVX TDK Murata AVX TDK GRM188R71H104KA93D 1 Murata Murata C1608X7R1H104K 100 pF, 50V, ceramic capacitor, NPO, 0603 AVX C1608X5R0J475M -- 1 Murata C1608X5R0J475M 06035C104KAT2A C22 TDK AVX 06036D105KAT2A C16, C18, C1608X5R0J105K C21, C23 GRM188R60J105KA01D 390 pF, 50V, ceramic capacitor, NPO, 0603 Murata TDK C15, C20, FP3-1R0-R C24 GRM188R60J106ME47D 1 AVX C3225X5R0J107M 06036D106MAT 39 pF, 50V, ceramic capacitor, NPO, 0603 Murata 12106D107MAT2A GRM32ER60J107ME20L C17 TDK AVX GRM31CR60J476ME19L 3 Murata TDK C3216X5R0J476M 1 nF, 50V, ceramic capacitor, X7R, 0603 AVX C1608C0G1H101J 12066D476MAT2A 1 Murata 06035A101JAT2A GRM1885C1H101JA01D C10, C11 TDK AVX GRM188R71H391KA01D 2.2F, 6.3V, ceramic capacitor, X5R, 0805 Murata TDK C1608C0G1H391J 3 AVX C1608C0G1H390J 06035A391JAT2A 22 F, 6.3V, ceramic capacitor, X5R, 0805 Murata 06035A390JAT2A GRM1885C1H390JA01D C8 TDK TDK C1608X7R1H102K Qty. Murata C2012X5R0J225K 06035C102KAT Description AVX 08056D225KAT2A GRM21BR60J225KA01L C4, C6, C12 Manufacturer -- AVX TDK Murata Panasonic Cooper MOSFET, N-CH 20V 7.4A 8-SOIC 2 R1A CRCW0603300RFKEA Vishay Dale Fairchild 300, resistor, 1%, 0603 1 R1B CRCW06031101FKEA Vishay Dale 510, resistor, 1%, 0603 1 R1C CRCW0603806RFKEA Vishay Dale 806, resistor, 1%, 0603 1 R1D CRCW06031K10FKEA Vishay Dale 1.1 k, resistor, 1%, 0603 1 2018 - 2019 Microchip Technology Inc. DS20006085B-page 23 MIC5166 TABLE 7-1: Item R2 BILL OF MATERIALS (CONTINUED) Part Number CRCW0603698RFKEA Manufacturer Vishay Dale Description Qty. 698, resistor, 1%, 0603 1 R3 CRCW06032002FKEA Vishay Dale 20 k, resistor, 1%, 0603 1 R4 CRCW06034752FKEA Vishay Dale 47.5 k, resistor, 1%, 0603 1 Vishay Dale 2.2, resistor, 1%, 0603 5 R6, R8, R11, R17, CRCW06032R20RFKEA R21 R7 CRCW060349R9RFKEA Vishay Dale 49.9, resistor, 1%, 0603 1 R9 CRCW06031002FKEA Vishay Dale 10 k, resistor, 1%, 0603 1 R10, R19 CRCW06031K00FKEA Vishay Dale 1 k, resistor, 1%, 0603 2 R12 CRCW0603000RFKEA Vishay Dale 0, resistor, 1%, 0603 1 Vishay Dale 1, resistor, 1.5W, 1%, 2512 3 R13, R14, CRCW25121R00FKEGHP R24 CRCW25122R00JNEG Vishay Dale 2, resistor, 1.5W, 1%, 2512 1 R16, R18, CRCW06031003FKEA R20 R15 Vishay Dale 100 k, resistor, 1%, 0603 3 R22, R23 Vishay Dale 0.5, resistor, 1.5W, 1%, 2512 2 Pot, 10 k, 0.5W, 9.6x5x10 1 RV1 LR2512-R50FW PV36W103C01B00 Murata U1 MIC22405YML Microchip 4A, Synchronous Buck Regulator 1 U2 MIC5166YMM Microchip 3A High-Speed Low VIN DDR Terminator 1 U3 SN74AHCT00RGYR Quad, 2IN Pos-NAND Gate, 14-pin, QFN 1 U4 MIC1557YM5 Microchip 5 MHz RC Timer Oscillator 1 U5 MIC4425 Microchip 3A Dual Inverting and Non-Inverting MOSFET Driver 1 DS20006085B-page 24 TI 2018 - 2019 Microchip Technology Inc. MIC5166 7.1 PCB Layout Recommendations FIGURE 7-4: Top Silk. FIGURE 7-5: Copper Layer 1. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 25 MIC5166 FIGURE 7-6: Copper Layer 2. FIGURE 7-7: Copper Layer 3. DS20006085B-page 26 2018 - 2019 Microchip Technology Inc. MIC5166 FIGURE 7-8: Copper Layer 4. FIGURE 7-9: Bottom Silk. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 27 MIC5166 8.0 PACKAGING INFORMATION 8.1 Package Marking Information Legend: XX...X Y YY WW NNN e3 * 10-Lead DFN* Example Y XXXX NNN Y 5166 288 Product code or customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. , , Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar () symbol may not be to scale. DS20006085B-page 28 2018 - 2019 Microchip Technology Inc. MIC5166 10-Lead 3 mm x 3 mm DFN Package Outline & Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 29 MIC5166 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS20006085B-page 30 2018 - 2019 Microchip Technology Inc. MIC5166 APPENDIX A: REVISION HISTORY Revision A (October 2018) * Converted Micrel document MIC5166 to Microchip data sheet template DS20006085A. * Minor grammatical text changes throughout. Revision B (March 2019) * EN and PG pin names/numbers corrected in Typical Application Circuit and Figure 7-2. * Updated VTT Accuracy values in the Electrical Characteristics table. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 31 MIC5166 NOTES: DS20006085B-page 32 2018 - 2019 Microchip Technology Inc. MIC5166 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: Device X XX -XX Part No. Junction Temp. Range Package Media Type Device: MIC5166: Junction Temperature Range: Y = -40C to +125C, RoHS-Compliant Package: ML = 10-Lead 3 mm x 3 mm x 0.9 mm DFN Media Type: TR = 5,000/Reel Note: a) MIC5166YML-TR: MIC5166, -40C to +125C Temperature Range, 10-Lead 3 mm x 3 mm DFN, 5,000/Reel 3A High-Speed, Low VIN DDR Terminator Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DFN is a green, RoHS-compliant package. Lead finish is NiPdAu. Mold compound is Halogen free. 2018 - 2019 Microchip Technology Inc. DS20006085B-page 33 MIC5166 NOTES: DS20006085B-page 34 2018 - 2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== 2018 - 2019 Microchip Technology Inc. The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018 - 2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4306-3 DS20006085B-page 35 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra'anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS20006085B-page 36 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 2018 - 2019 Microchip Technology Inc. 08/15/18